An example of conventional open drain circuit is shown in FIG. 1. The open drain circuit of a FIG. 1 comprises a package 10 having an output terminal 12 and a common (ground) terminal 14. The output terminal 12 is coupled through a load resistor 16 to an external voltage supply 18 providing a power of +V.sub.TT, and the common terminal 14 is grounded. The load resistor 16 forms a load capacitance 20 between the output terminal 12 and the common terminal 14.
The drain region of an output transistor 22, an N-channel MOSFET in this case, is connected through a transmission line to the output terminal 12, and the source region of the output transistor 22 is connected through a transmission line to the common terminal 14. The connection of the output transistor 22 by the transmission lines produces parasitic inductances 24 and 26 between the drain region and the output terminal and between the source region and the common terminal 14, respectively. Although not shown, at least a portion of the package 10 is a metallic portion which provides a reference potential point, and parasitic capacitances 28 and 30 are exhibited between the metallic portion and the drain region and between the metallic portion and the source region, respectively.
A control voltage is applied between the gate and source regions of the output transistor 22 through two stages of inverters 32 and 34. The inverter 32 comprises a P-channel MOSFET 32P and an N-channel MOSFET 32N. The drain of the MOSFET 32P is connected to the drain of the MOSFET 32N, the source of the MOSFET 32P is connected to a voltage supply 36 of +V.sub.DD within the package 10, and the source of the MOSFET 32N is connected to the source region of the output transistor 22.
Similarly, the inverter 34 comprises a P-channel MOSFET 34P and an N-channel MOSFET 34N, with the drains of the MOSFET's 34P and 34N connected together, with the source of the MOSFET 34P connected to the V.sub.DD voltage supply 36, and with the source of the MOSFET 34N connected to the source region of the output transistor 22.
The output node of the inverter 34, i.e. the junction of the drains of the P-channel and N-channel MOSFET's 34P and 34N is coupled to the gate region of the output transistor 22. The output node of the inverter 32, i.e. the junction of the drains of the MOSFET's 32P and 32N, is coupled to the gate regions of the MOSFET's 34P and 34N. An input voltage is applied to the gate regions of the MOSFET's 32P and 32N via an input terminal 38. The input voltage assumes two values, H and L, which correspond respectively to +V.sub.DD and ground potential.
In the above-stated arrangement, with the parasitic inductances 24 and 26 and the parasitic capacitances 28 and 30 not being not taken into consideration, when an H-level input signal is applied, the P-channel MOSFET 32P is non-conductive, and the N-channel MOSFET 32N is conductive so that an L-level signal is applied as an output of the inverter 32 to the gate regions of the P-channel MOSFET 34P and N-channel MOSFET 34N. As a result, the MOSFET 34P becomes conductive, while the MOSFET 34N is non-conductive. This causes the output transistor 22 to become conductive so that current I.sub.D will flow from the external power supply 18 into the output transistor 22. When the resistance value of the load resistor 16 is R.sub.L, the voltage at the output terminal 12 is +V.sub.TT -I.sub.D .multidot.R.sub.L, i.e. the L-level.
Conversely, when the input voltage at the input terminal 38 is at the L-level, the output signal of the inverter 32 is at the H-level, and the output signal of the inverter 34 is at the L-level, which results in the non-conduction of the output transistor 22 so that the voltage at the output terminal 12 is at +V.sub.TT or H-level.
In the above discussion, the parasitic inductances 24 and 26 and the parasitic capacitances 28 and 30 have not been taken into account. Actually, however, these factors influence the operation of the circuit so that when the input voltage at the input terminal 38 changes from the H-level to the L-level, overshoot, undershoot and ringings may disadvantageously be produced in the output signal at the output terminal 12 and in the signal at the source region of the output transistor 22.
Specifically, when the input voltage at the terminal 38 is at the H-level, the output transistor 22 is conductive so that current flows from the power supply 18 to the load resistor 16, which current is divided into portions flowing into the load capacitance 20 and the parasitic inductance 24. The current flowing through the parasitic inductance 24 is further divided into portions flowing into the parasitic capacitance 28 and the output transistor 22. The current flowing into the output transistor 22 is further divided into portions flowing into the parasitic capacitance 30 and the parasitic inductance 26. Thus, while these currents are flowing, energy is stored in the parasitic inductance 24 and 26 and in the load capacitance 20, and parasitic capacitance 28 and 30.
When the input voltage at the input terminal 38 begins to change from the H-level to the L-level at a time t.sub.6, as shown in FIG. 2(a), the gate voltage of the output transistor 22 will change from the H-level to the L-level at a time delayed from the time t.sub.6 by a time period required for the input voltage to pass through the inverters 32 and 34, as shown in FIG. 2(b). This change in the gate voltage of the output transistor 22 causes current flowing between the drain and the source of the output transistor 22 to change, which results in the discharge of energy stored in the parasitic inductances 24 and 26 and the load capacitances 20, and parasitic capacitances 28 and 30. During a time when the gate voltage of the output transistor 22 is changing from the H-level to the L-level, a relatively long time is required for the energy to decrease since the resistance value exhibited between the source and drain of the output transistor 22 is relatively small. As a result, an overshoot and an undershoot are generated in the voltage at the output terminal 12 as shown in FIG. 2(c), and ringings are generated in the voltage at the source region of the output transistor 22 as shown in FIG. 2(d).
During a period when the input voltage at the input terminal 38 is at the L-level, current flowing from the power supply 18 into the load resistor 16 is divided into two portions, one flowing into a circuit branch including the parasitic inductances 24 and 26 and the parasitic capacitances 28 and 30 and the other flowing into a branch including the load capacitance 20. Energy has been stored in the parasitic inductances 24 and 26 and in the parasitic capacitances 28 and 30 and load capacitance 20. When the input voltage at the input terminal 38 changes from the L-level to the H-level at a time t.sub.7 as shown in FIG. 2(a), the output output transistor 22 is rendered conductive and current begins to flow between the drain and source of the transistor 22. At the beginning of this transition of the input voltage from the L-level to the H-level, the drain-source resistance of the output transistor 22 is large, and, therefore, the energy stored in the parasitic inductances 24 and 26 and the load capacitance 20, and parasitic capacitances 28 and 30 is released through this large drain-source resistance. Thus, the energy is attenuated in a relatively short time period. Accordingly, as shown in FIGS. 2(c) and 2(d), after the time t.sub.7, no significant overshoot, undershoot or ringings occur in the voltage at the output terminal 12 and in the voltage at the source region of the output transistor 22.
As described above, conventional open drain output circuit have a problem that large overshoot, undershoot and ringings occur when the input voltage and, hence, the control voltage change from the H-level to the L-level.